AOT502 clamped n-channel mosfet general description product summary v ds i d (at v gs =10v) 60a r ds(on) (at v gs =10v) < 11.5m ? 100% uis tested 100% r g tested symbol v ds v gs i dm i as, i ar e as, e ar t j , t stg symbol t 10s steady-state steady-state r jc maximum junction-to-case c/w c/w maximum junction-to-ambient a d 1.6 65 1.9 t c =100c w power dissipation a p dsm w t a =70c 79 1.2 t a =25c power dissipation b 28.5 a t a =25c i dsm a t a =70c i d 60 41 t c =25c absolute maximum ratings t a =25c unless otherwise noted AOT502 uses an optimally designed temperature compensated gate-drain zener clamp. under overvoltage conditions, the clamp activates and turns on the mosfet, safely dissipating the energy in the mosfet. the built in resistor guarantees proper clamp operation under all circuit conditions, and the mosfet never goes into avalanche breakdown. advanced trench technology provides excellent low rdson, gate charge and body diode characteristics, making this device ideal for motor and inductive load control applications. avalanche energy l=0.1mh c mj avalanche current c 7 continuous drain current 41 9 a v maximum units parameter c thermal characteristics units maximum junction-to-ambient a c/w r ja 13 54 15.6 parameter typ max t c =25c 1.9 39 t c =100c junction and storage temperature range -55 to 175 p d clamped 137 pulsed drain current c continuous drain current v clamped gate-source voltage drain-source voltage clamped to220 top view bottom view g s d g d s d g 10 ? s d g 10 ? s d rev1: may 2009 www.aosmd.com page 1 of 7
AOT502 symbol min typ max units bv dss(z) 33 v bv clamp 36 44 v i dss(z) 20 a bv gss 20 v i gss 10 ? q g 18.5 23.4 28 nc q gs 2.7 3.4 4 nc q gd 4 7 10 nc t d(on) 13.5 ns t r 17.5 ns t d(off) 63 ns t f 27 ns t rr 14 17.5 21 ns q rr 53.5 67 80 nc components in life support devices or systems are not authorized. aos does not assume any liability arising out of such applications or uses of its products. aos reserves the right to improve product design, functions and reliability without notice. v gs =0v, v ds =15v, f=1mhz switching parameters drain-source breakdown voltage on state drain current i d =10ma, v gs =0v v gs =10v, v ds =5v v ds =v gs , i d =250 a v ds =0v, v gs =10v gate-body leakage current gate-source voltage electrical characteristics (t j =25c unless otherwise noted) static parameters parameter conditions v ds =0v, i d =250 a gate threshold voltage maximum body-diode continuous current diode forward voltage r ds(on) static drain-source on-resistance forward transconductance v gs =10v, i d =30a m ? i s =1a, v gs =0v v ds =5v, i d =30a dynamic parameters turn-on rise time turn-off delaytime v gs =10v, v ds =15v, r l =0.5 ? , r gen =3 ? gate resistance v gs =0v, v ds =0v, f=1mhz turn-off fall time total gate charge v gs =10v, v ds =15v, i d =30a gate source charge body diode reverse recovery charge i f =30a, di/dt=750a/ s input capacitance output capacitance turn-on delaytime gate drain charge body diode reverse recovery time reverse transfer capacitance i f =30a, di/dt=750a/ s drain-source clamping voltage i d =1a, v gs =0v zero gate voltage drain current v ds =16v, v gs =0v a. the value of r ja is measured with the device mounted on 1in 2 fr-4 board with 2oz. copper, in a still air environment with t a =25c. the power dissipation p dsm is based on r ja and the maximum allowed junction temperature of 150c. the value in any given application depends on the user's specific board design, and the maximum temperature of 175c may be used if the pcb allows it. b. the power dissipation p d is based on t j(max) =175c, using junction-to-case thermal resistance, and is more useful in setting the upper dissipation limit for cases where additional heatsinking is used. c. repetitive rating, pulse width limited by junction temperature t j(max) =175c. ratings are based on low frequency and duty cycles to keep initial t j =25c. d. the r ja is the sum of the thermal impedence from junction to case r jc and case to ambient. e. the static characteristics in figures 1 to 6 are obtained using <300 s pulses, duty cycle 0.5% max. f. these curves are based on the junction-to-case thermal impedence which is measured with the device mounted to a large heatsi nk, assuming a maximum junction temperature of t j(max) =175c. the soa curve provides a single pulse rating. g. these tests are performed with the device mounted on 1 in 2 fr-4 board with 2oz. copper, in a still air environment with t a =25c. rev1: may 2009 www.aosmd.com page 2 of 7
AOT502 typical electrical and thermal characteristic s 17 5 2 10 0 18 40 0 20 40 60 80 2 2.5 3 3.5 4 4.5 5 v gs (volts) figure 2: transfer characteristics (note e) i d (a) -40c 4 6 8 10 12 14 0 5 10 15 20 25 30 i d (a) figure 3: on-resistance vs. drain current and gate voltage (note e) r ds(on) (m ? ) 1.0e-05 1.0e-04 1.0e-03 1.0e-02 1.0e-01 1.0e+00 1.0e+01 1.0e+02 0.0 0.2 0.4 0.6 0.8 1.0 1.2 v sd (volts) figure 6: body-diode characteristics (note e) i s (a) 25c 125c -40c 0.4 0.8 1.2 1.6 2 2.4 -50 0 50 100 150 200 temperature (c) figure 4: on-resistance vs. junction temperature (note e) normalized on-resistance v gs =10v i d =30a 0 10 20 30 40 50 246810 v gs (volts) figure 5: on-resistance vs. gate-source voltage (note e) r ds(on) (m ? ) 25c 125c v ds =5v v gs =10v i d =30a 25c 125c 0 20 40 60 80 100 120 140 012345 v ds (volts) fig 1: on-region characteristics (note e) i d (a) v gs =3.5v 4v 6v 7v 10v 4.5v 5v rev1: may 2009 www.aosmd.com page 3 of 7
AOT502 typical electrical and thermal characteristic s 17 5 2 10 0 18 40 0 2 4 6 8 10 0 5 10 15 20 25 q g (nc) figure 7: gate-charge characteristics v gs (volts) 0 200 400 600 800 1000 1200 1400 1600 1800 0 5 10 15 20 25 30 v ds (volts) figure 8: capacitance characteristics capacitance (pf) c iss 0 200 400 600 800 1000 0.0001 0.001 0.01 0.1 1 10 pulse width (s) figure 10: single pulse power rating junction-to- case (note f) power (w) 0.001 0.01 0.1 1 10 0.000001 0.00001 0.0001 0.001 0.01 0.1 1 10 pulse width (s) figure 11: normalized maximum transient thermal impedance (note f) z jc normalized transient thermal resistance c oss c rss v ds =15v i d =30a single pulse d=t on /t t j,pk =t c +p dm .z jc .r jc t o n t p d in descending order d=0.5, 0.3, 0.1, 0.05, 0.02, 0.01, single pulse t j(max) =175c t c =25c 10 v ds (volts) i d (amps) figure 9: maximum forward biased safe operating area (note f) 10 jc =1.9c/w rev1: may 2009 www.aosmd.com page 4 of 7
AOT502 typical electrical and thermal characteristic s 17 5 2 10 0 18 40 0.001 0.01 0.1 1 10 0.0001 0.001 0.01 0.1 1 10 100 1000 pulse width (s) figure 16: normalized maximum transient thermal impedance (note h) z ja normalized transient thermal resistance sin g le pulse d=t on /t t j,pk =t a +p dm .z ja .r ja t on t p d in descending order d=0.5, 0.3, 0.1, 0.05, 0.02, 0.01, single pulse 10 100 1000 1 10 100 1000 time in avalanche, t a (us) figure 12: single pulse avalanche capability (note c) i ar (a) peak avalanche current 0 20 40 60 80 100 0 25 50 75 100 125 150 175 t case (c) figure 13: power de-rating (note f) power dissipation (w) 0 20 40 60 80 0 25 50 75 100 125 150 175 t case (c) figure 14: current de-rating (note f) current rating i d (a) t a =25c 1 10 100 1000 10000 0.00001 0.001 0.1 10 1000 pulse width (s) figure 15: single pulse power rating junction-to- ambient (note h) power (w) t a =25c t a =150c t a =100c t a =125c r ja =65c/w rev1: may 2009 www.aosmd.com page 5 of 7
AOT502 typical protection characteristic s 0.00 0.50 1.00 1.50 2.00 30 35 40 45 v ds (volts) fig 15: bv clamp characteristic i d (a) bv dss(z) bv clamp 0.00 10.00 20.00 30.00 40.00 50.00 60.00 0.00e+0 0 2.50e- 05 5.00e- 05 7.50e- 05 1.00e- 04 1.25e- 04 time in avalanche (seconds) fig 16: unclamped inductive switching id (a)/ vds(v) bv clamp 100 o c trench bv bv clamp 25 o c fig16: the built-in gate to drain clamp prevents the device from going into avalanche by setting the clamp voltage well below the actual breakdown of the device. when the drain to gate voltage approaches the bv clamp, the internal gate to source voltage is charged up and channel conduction occurs, sinking the current safely through the device. the bv clamp is virtually temperature independent, providing even greater protection during normal operation. this device uses built-in gate to source and gate to drain zener protection. while the gate-source zener protects against excessive v gs conditions, the gate to drain protection, clamps the v ds well below the device breakdown, preventing an avalanche condition within the mosfet as a result of voltage over-shoot at the drain electrode. it is designed to breakdown well before the device breakdown. during such an event, current flows through the zener clamp, which is situated internally between the gate to drain. this current flows at bv dss(z) , building up the v gs internal to the device. when the current level through the zener reaches approximately 300ma, the v gs is approximately equal to v gs(plateau) , allowing significant channel conduction and thus clamping the drain to source voltage. the v gs needed to turn the device on is controlled with an internally lumped gate resistor r approximately equal to 10 ? . v gs(plateau) = 10 ? x 300ma =3v it can also be said that the vds during clamping is equal to: bv dss = bv clamp + v gs(plateau) a dditional power loss associated with the protection circuitry can be considered negligible when compare to the conduction losses of the mosfet itself; ex: pl=30amax x 16v=0.48mw (zener leakage loss) pl(rds)=10 2 a x 6m ? =300mw (mosfet loss) r d + + - vz g v plateau - s + - s + - rev1: may 2009 www.aosmd.com page 6 of 7
AOT502 - + vdc ig vds dut - + vdc vgs vgs 10v qg qgs qgd charge gate charge test circuit & waveform - + vdc dut vdd vgs vds vgs rl rg vgs vds 10% 90% resistive switching test circuit & waveforms tt r d(on) t on t d(off) t f t off vdd vgs id vgs rg dut - + vdc l vgs vds id vgs bv i unclamped inductive switching (uis) test circuit & waveforms ig vgs - + vdc dut l vds vgs vds isd isd diode recovery test circuit & waveforms vds - vds + i f ar dss 2 e = 1/2 li di/dt i rm rr vdd vdd q = - idt ar ar t rr rev1: may 2009 www.aosmd.com page 7 of 7
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